A phase detector circuit that is used for extracting a clock from a random NRZ (Non-Return-To-Zero) signal to recover the signal is required to have (1) a mechanism for preventing a significant loss of lock when consecutive identical digits (CIDs) included in the random NRZ signal are input and (2) a linearity of a phase to voltage conversion characteristic around phase-locked point. Here, the random NRZ signal is in the form of a pulse code in which a pulse width equals to a length of a code. The above-described requirement (1) is mainly intended for preventing a significant reduction in a bit error rate of the recovered signal, and the requirement (2) is mainly intended for realizing a high quality of the extracted clock.
In order to address the requirement (1), that is, in order to prevent a significant loss of lock when the CIDs are input, the phase detector circuit often uses a method of not outputting any waveform when the CIDs are input. In order to address the requirement (2), that is, in order to assure the linearity of the phase to voltage conversion characteristic around phase-locked point, it is required to maintain a limited pulse width of the output waveform of the phase detector circuit under phase-locked condition.
FIG. 13 is a circuit diagram of a conventional phase detector circuit used for clock extraction and signal recovery. In FIG. 13, reference numeral 80 denotes a phase detector circuit, reference numerals 81 and 82 denote a pair of differential input terminals for the random NRZ signals, reference numerals 83 and 84 denote a pair of differential input terminals for the random NRZ signals that have the same pattern as those of the signals input to the terminals 81 and 82 and are delayed therefrom by θ in phase, reference numerals 85 and 86 denotes a pair of differential input terminals for the random NRZ signals that are delayed from the signals input to the terminals 81 and 82 by T/2, which is a half of the period T of the signals input to the terminals 81 and 82, reference numerals 91 and 92 denote a pair of differential output terminals of the phase detector circuit 80, reference numerals 87 denotes a terminals of a high potential power supply (Vcc), reference numeral 88 denotes a terminal of a low potential power supply (G), reference numerals 93 (R1) and 94 (R2) denote resistances, reference numerals 71 to 78 denote bipolar transistors, and reference numerals 95 and 96 denote low current circuits. See the reference: N. Ishihara and Y. Akazawa, “A Monolithic 156 Mb/S Clock and Data recovery PLL Circuit Using the Sample-and-Hold Technique”, IEEE J. Solid State Circuits, Vol. 29, pp. 1566-1571, December 1994.
FIG. 14 is a timing chart of a PLL circuit using the phase detector circuit 80 shown in FIG. 13. As shown in FIG. 14(A), the random NRZ signals are input to the pair of the differential terminals 81 and 82 of the phase detector circuit 80, and as shown in FIG., 14(B), the random NRZ signals having the same pattern as shown in FIG. 14(A) and delayed by θ in phase are input to the pair of the differential terminals 83 and 84. As a result, as shown in FIG. 14(C), signal having a pulse width a associated with the phase difference θ are output from the pair of the output differential terminals 91 and 92 of the PLL circuit 80. In the PLL circuit circuit, a negative feedback is provided to attain the phase difference of 180 degrees, that is, to provide a delay of T/2, which is a half of the period of the random NRZ signal, and consequently, as shown in FIG. 14(C), the pulse width a at the pair of the output differential terminals 91 and 92 is reduced as the phase-locked state is approached. As shown in FIGS. 14(A) to 14(C), the phase detector circuit 80 cannot physically cope with a pulse width less than a predetermined value due to an effect of capacitance or the like, and thus cannot maintain the accuracy thereof.
FIG. 15 shows a phase to voltage conversion characteristic of the conventional phase detector circuit 80. In FIG. 15, the vertical axis represents a DC voltage component at the pair of the differential terminals 91 and 92, and the horizontal axis represents the phase difference described above. As shown in FIG. 15, while the phase to voltage conversion characteristic is ideally represented by the dotted line, the linearity thereof is compromised in the phase detector circuit 80, which exhibits the characteristic with distortion. If such a phase detector circuit 80 having the linearity of the phase to voltage conversion characteristic compromised is used in the PLL circuit for clock extraction and signal recovery, the phase detector circuit 80 cannot accurately detect the phase difference, so that a time-base variation in the waveform, which is referred to as a jitter, appears in the clock extracted.
As described above, there is a problem that the clock extracted from the PLL circuit using the phase detector circuit of poor linearity of the phase to voltage conversion characteristic is significantly inferior in the quality as a clock.